A specialized field, commonly referred to as “electronic design automation” (EDA), has evolved to handle the demanding and complicated task of designing, laying out and verifying integrated circuit (IC) semiconductor chips. In EDA, computers are extensively used to automate the design, layout and verification process. The first step of the EDA design process typically involves the formal specification of the design, using hardware design languages such as Verilog or VHDL, and synthesis of the design into netlists of devices to be placed and routed. Typically, the synthesized design is stored on a computer tape or disk. The next step of the process typically involves the use of circuit simulation software to test the synthesized design of the IC to see if it operates as needed.
Once the IC design has been verified through computer simulation, the third step in the EDA design process is the use of layout software to generate component placement and interconnections for the components. However, before fabrication on the semiconductor chip begins, extensive further verification and/or testing are typically performed to further verify and check that the IC has been properly designed and physically laid out. This is accomplished in a fourth step of the EDA design process wherein design checks are performed, and IC simulation software and/or emulation system are used to test the operation and performance of the proposed IC. A pre-defined set of rules are also stored. These rules may specify certain dimensions and other criteria for checking to determine whether the new design has been properly laid out. Thereafter, simulation and/or emulation may be performed. Hence, new designs and layouts are subject to a host of rigorous verification and testing procedures, including procedures which check the physical layout to ensure that it meets certain well-established rules or guidelines.
Often, several iterations of the design, layout, and verification process are required in order to optimize the IC's size, cost, heat output, speed, power consumption, and electrical functionalities. After the IC design has been established to be good, the fifth step in the EDA process involves the use of mask fabrication software to generate masks for manufacturing the ICs, which are then used to manufacture IC prototypes. These IC prototypes are further tested by automated test equipment (ATE).
The use of asymmetric transistors in SOI technologies is now widespread, and one major implementation issue is the impact the use of asymmetric FET has on the design and layout of the integrated circuit. Typically, block mask shapes that define the asymmetric FETs must be placed in the design in every instance an asymmetric FET is required. This alone is not sufficient, as the asymmetric FET will be either ‘source up’ or ‘source down’ (when the poly gates are restricted to be only horizontal, as is common in CMOS technologies at the 90 nm node and beyond). The two possible FET orientations for every instance of design cell mean that just identifying sources is not enough. It is also necessary to identify, relative to the wafer notch, if the source is on the top or bottom. To accomplish this in design is impractical, as design is hierarchical.